{
	"title": "PCN0603 Cyclone® II Family M4K Memory Block Modification",
	"id": "677525",
	"created_at": "2021-10-12T15:57:47+00:00",
	"modified_at": "2006-04-12T07:00:00+00:00",
	"description": "The M4K memory block used in the Cyclone™ II device family is being modified to prevent write errors that may occur under a rare set of conditions when configured in dual-port, dualclock mode.",
	"download_url": "https://docs.altera.com/api/khub/documents/9yrNH5BkNoPoGQYM8UXHig/content",
	"original_url": "https://cdrdv2.intel.com/v1/dl/getContent/677525?explicitVersion=true",
	"html_url": "https://intel.com/content/www/us/en/content-details/677525/pcn0603-cyclone-ii-family-m4k-memory-block-modification.html",
	"url": "https://intel.pcn.captnemo.in/pcn/677525",
	"category": "Product Change Notifications (PCN)",
	"self": "https://intel.pcn.captnemo.in/api/677525.json"
}